It’s not handled, we just ignore SysEx start (0xF0) to SysEx end (0xF7).
I think it could be added easily, we could split it up in chunks like you say, I don’t think it would be hard.
I did it that way to avoid allocations, and so the MIDI frames can be aligned to audio frames.
It just sends to the first one it finds, which I know is not ideal. Supporting multiple ports would be contained in this PR for USB hubs. But we would still need a MIDI device and port “chooser”. I was thinking something along the lines of the File Browser, where a module can call as async function to have a window pop open with a list of attached devices.
Correct. Some good ideas for their implementation here: Support for VCV expander modules, with proposed design
It might offer a boost for that expander/main-module combo, but not necessarily for the entire patch.
But you would still want some sort of sharing mechanism if a module and its expander are both accessing the same block of data, right? E.g. the producer/consumer message system in VCV. Or do what the Venom modules do and have the main module be the only thing that accesses the data (so, no sharing at all).
Hmm… I’m not sure but I would hope we can handle it like we handle cables: First process the same-core cables in parallel on each core, and then sync the cores with a barrier, and then process the cables that cross cores in parallel on each core, then sync again (so the processes are always reading from different cores and writing to different cores).
The SCU unit on the A7 that handles sharable memory between the two A7 cores is poorly documented, and by “poorly” I mean there is only a tiny amount of generic docs for a related architecture, and it’s inaccurate… so that’s the source of my uncertainty!
Re: core affinity: since a late v2.0-dev release, core affinity is dynamic, and can be re-assigned anytime a module is added or removed, or the patch is loaded/re-loaded. Basically we run the patch a few times and measure each module and its cables, then come up with a partition that gives fairly equal times between cores.